`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   23:47:52 05/04/2013
// Design Name:   Execution_Control
// Module Name:   C:/Users/jboedin/Desktop/LAB2/ec_tb.v
// Project Name:  LAB2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Execution_Control
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_Execution_Control;

	// Inputs
	reg go;
	reg ram_clk;
	reg cpu_clk;
	reg stop;
	reg rst;

	// Outputs
	wire pop_data;

	// Instantiate the Unit Under Test (UUT)
	Execution_Control uut (
		.go(go), 
		.Sys_clk_100mhz(ram_clk), 
//		.cpu_clk(cpu_clk), 
		.stop(stop), 
		.rst(rst), 
		.pop_data(pop_data)
	);

	initial begin
		ram_clk = 1'b1;
		forever #50 ram_clk <= ~ram_clk;
	end
	
	initial begin
		cpu_clk = 1'b1;
		forever #100 cpu_clk <= ~cpu_clk;
	end


	initial begin
		// Initialize Inputs
		go = 1;
		ram_clk = 0;
		cpu_clk = 0;
		stop = 0;
		rst = 1;

		// Wait 100 ns for global reset to finish
		#150;
        
		// Add stimulus here
		go = 0; #1500000;
			
		stop = 1'b1;
	
	end
      
endmodule

